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asix electronics corporation 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://ww w.asix.com.tw AX88875AP 10/100base dual speed bripeater controller asix asix AX88875AP 10/100base 5-port dual speed ? bripeater ? controller data sheets (10/16/ ? 00) document no . : ax875a-06.doc this data sheets contain new products information. asix electronics reserves the rights to modify the products specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. always contact asix for possible updates before starting a design.
AX88875AP bripeater asix electronics corporation 2 contents 1.0 ax88875a overview ................................ ................................ ................................ ................................ ..... 3 1.1 g eneral d escription ................................ ................................ ................................ ................................ ...... 3 1.2 f eatures ................................ ................................ ................................ ................................ .......................... 4 1.3 b lock d iagram ................................ ................................ ................................ ................................ ............... 5 1.4 p in c onnection d iagram (m ode 0) ................................ ................................ ................................ ................ 6 1.5 p in c onnection d iagram (m ode 1) ................................ ................................ ................................ ................ 7 2.0 pin description ................................ ................................ ................................ ................................ ........... 8 2.1 mii interfaces ................................ ................................ ................................ ................................ ................ 8 2.2 led d isplay ................................ ................................ ................................ ................................ .................... 9 2.3 b uffer memory pins group ................................ ................................ ................................ ........................... 10 2.4 m iscellaneous ................................ ................................ ................................ ................................ .............. 11 2.5 p ower on configuration setup signals cross reference table ................................ ................................ 12 3.0 functional description ................................ ................................ ................................ ..................... 13 3.1 r epeater s tate m achine ................................ ................................ ................................ .............................. 13 3.2 rxe /txe control ................................ ................................ ................................ ................................ ... 13 3.3 j abber s tate m achine ................................ ................................ ................................ ................................ .. 14 3.4 p artition s tate m achine ................................ ................................ ................................ ............................. 14 3.5 led d isplay i nterface ................................ ................................ ................................ ................................ 14 4.0 internal registers ................................ ................................ ................................ ................................ 16 4.1 c onfiguration r egister (config) ................................ ................................ ................................ ............. 16 5.0 electrical specification and timing ................................ ................................ .......................... 17 5.1 a bsolute m aximum r atings ................................ ................................ ................................ ........................ 17 5.2 g eneral o peration c onditions ................................ ................................ ................................ ................... 17 5.3 dc c haracteristics ................................ ................................ ................................ ................................ ..... 17 5.4 ac specifications ................................ ................................ ................................ ................................ ......... 18 5.4.1 mii interface timing tx & rx ................................ ................................ ................................ .................. 18 5.4.2 sram read cycle and write cycle ................................ ................................ ................................ ............. 19 5.4.3 led display ................................ ................................ ................................ ................................ ......... 20 5.4.4 led display after reset ................................ ................................ ................................ .......................... 20 6.0 package information ................................ ................................ ................................ ........................... 21 appendix a: applications ................................ ................................ ................................ .......................... 22 a.1 s tand - along 5- ports 10/100m bps hub a pplication ................................ ................................ ................. 22 a.2 s tand - along 4- ports 10/100m bps hub with one mac a pplication ................................ ........................ 22 appendix b: using mii i/f connects to mac ................................ ................................ ...................... 23 figures f ig - 1 c hip b lock d iagram ................................ ................................ ................................ ................................ ..... 5 f ig - 2 p in c onnection d iagram (m ode 0) ................................ ................................ ................................ .............. 6 f ig - 3 p in c onnection d iagram (m ode 1) ................................ ................................ ................................ .............. 7 f ig - 4 a pplication for led display ................................ ................................ ................................ ..................... 15 f ig - 5 s tand - along 5- ports 10/100m bps hub a pplication ................................ ................................ ................ 22 f ig - 6 s tand - along 4- ports 10/100m bps hub with one mac a pplication ................................ ....................... 22
AX88875AP bripeater asix electronics corporation 3 1.0 ax88875a overview the ax88875a 10/100mbps dual speed ? bripeater ? controller is ? a dual speed repeater with build in bridge function ? it is design for low cost dumb hub application. the ax88875a directly supports up-to five 10/100mbps automatic links mii interfaces specially for soho market. the ax88875a is designed base on ieee 802.3u clause 27 ? repeater for 100mb/s base-band networks ? it is fully compatible with ieee 802.3u standard. 1.1 general description the ax88875a repeater controller is a subset of a repeater set containing all the repeater-specific components and functions, exclusive of phy components and functions. the ax88875a has five media independent interfaces (mii) to connect to phy or mac devices. the ax88875a supports 5 mii interfaces ports, a bridge packet buffer sram interface and led display interface. ax88875a without support expansion port to cascade to other ax88850 and ax88860 pure 100mbps repeater chips . . the ax88875a supports stand along 10/100mbps dual speed repeater applications with two led display mode. the ax88871a has two led display mode. mode 0 direct led display mode. mode 1 rich led display mode.
AX88875AP bripeater asix electronics corporation 4 1.2 features ieee 802.3u repeater compatible supports per port 10/100mbps alternative with auto detected build in 10/100mbps bridge engine with following features 1. minimum 32k bytes, maximum 128k bytes sram to buffer packets 2. seamless buffer management without waste any space of buffer memory 3. simple asynchronous 8-bit sram interface to reduce system cost 4. 256 or 1024 entries is supported 5. auto learning and filtering 6. two forwarding modes are supported : store-n-forward and fragment-free 7. flow-control is supported optionally. 8. buffer ram auto testing 9. routing and learning at wire speed (148810 packets/sec at 100mbps) supports 5 10/100mbps network connections 5 dedicated mii interfaces can support 100base-tx/t4/fx phy interfaces 5 th port can connect to bridge, switch or mac type device optionally. low latency design supports class ii repeater implementation all ports can be separately isolated or partitioned in response to fault condition separate jabber and partition state machines for each port per-port led display for jabber, partition, activity. global partition, ram test fail and collision, utilization (%) for 10/100mbps presentation power on led diagnosis. all the led display will follow the ? on-off-on-off-normal ? operation procedure during/after power on reset 160-pin pqfp
AX88875AP bripeater asix electronics corporation 5 1.3 block diagram fig - 1 chip block diagram 10/100 q-phy 10/100 phy or mac mii i/f mii interface re- concilia - tion sub-layer (port 0 - port 4 ) speed detection circuit elasticity buffer for 100mbps and 10mbps mux repeater state machine of 100mbps collision handling logic for 100mbps and10mbps per port jabber ctl , auto-partition sm & per port collision , partition counters. registers mib i/f (reserved) cascade arbitration logic of 100mbps (reserved) ........ mii i/f repeater state machine of 10mbps 100 mbps to 10mbps bridge mem i/f ( reserved)
AX88875AP bripeater asix electronics corporation 6 1.4 pin connection diagram (mode 0) fig - 2 pin connection diagram (mode 0) note : power on configuration setup signals refer section 2.5 cross referance table col[2] 35 38 bmd[2] 52 col_o[4] rxd[1][2] 130 vdd rxd[3][0] 68 159 25 145 31 42 txd[4][1] 32 143 129 txd[4][3] rxdv[3] vss1 bma[6] crs[0] txen[1] 141 txer[2] 71 txd[3][1] bmd[4] 77 101 bma[7] 63 mdc rxd[3][1] 78 vdd bma[12] col[4] col[0] 102 133 rxd[2][1] 146 121 rxer[0] 100 rxdv[2] txd[2][1] 56 142 rxd[0][2] 109 bma[15] 115 66 105 rxclk[4] txer[0] /lpart[4] 88 97 120 39 93 153 txen[0] 98 116 17 11 4 19 91 156 139 rxd[4][0] txd[2][3] /luti[4] col[3] 84 86 47 69 bmd[0] 29 bmd[5] 85 rxclk[1] 124 45 test1 134 vss1 mclk 37 40 2 bmd[7] /bmwr txd[0][1] 28 txd[0][2] 59 138 vss1 txd[1][3] rxd[1][0] crs[1] bma[4] 54 118 18 50 txd[2][2] rxer[3] 150 txd[0][3] vdd1 110 vss1 22 87 53 bma[2] 147 vdd 33 bma[5] 117 140 AX88875AP ( mode 0 ) 14 rxd[1][1] 125 44 96 152 vss 9 34 90 txen[2] 81 104 vss rxd[4][2] 128 vdd1 vdd 3 148 crs[2] 70 bma[0] 76 73 5 46 bma[16] /rst /lcol100 89 txd[1][2] bma[8] bma[14] 99 16 57 lclk txer[3] 20 bma[13] mdo txd[3][0] bma[10] 58 62 60 107 21 26 rxer[4] /lcol10 vdd 119 bma[3] rxd[2][2] txd[3][2] 49 rxd[3][3] 65 bma[1] 8 24 txd[1][1] vdd 127 67 135 bmd[1] /bma[15] 55 vdd1 rxd[4][3] 136 132 txd[4][2] 112 83 rxd[3][2] 41 122 92 51 72 74 113 txd[1][0] txer[4] 106 /half10 15 43 txen[3] 149 rxdv[1] 30 48 txen[4] 10 txd[4][0] rxd[4][1] rxclk[0] 108 23 144 155 rxd[2][3] 6 82 bma[11] 61 txer[1] rxd[1][3] 64 col[1] bmd[6] /luti[3] 158 rxer[1] 126 crs[3] 36 rxclk[3] vss vdd1 rxd[0][3] crs[4] 131 bmd[3] vss vdd rxer[2] rxd[0][1] txd[2][0] vss 103 137 rxd[2][0] /lsel10 rxdv[4] 95 txd[3][3] 154 txd[0][0] rxd[0][0] 7 151 vss 160 rxdv[0] 114 27 80 79 rxclk[2] 1 94 157 111 vss 13 75 bma[9] 12 123 vss vss /lpart[3] /lpart[2] /lpart[1] /lpart[0] /lact[4] /lact[2] /lact[3] /lact[0] /lact[1] nc nc /test2 /luti[5] /luti[2] /luti[1] /luti[0] pull_dn pull_dn pull_dn nc pull_dn pull_dn set1 set2 set0
AX88875AP bripeater asix electronics corporation 7 1.5 pin connection diagram (mode 1) fig - 3 pin connection diagram (mode 1) note : power on configuration setup signals refer section 2.5 cross referance table nc rxclk[2] rxd[2][0] crs[3] 144 txer[4] 55 119 57 148 125 33 54 vss1 153 txd[2][1] bma[7] txd[4][1] vss rxdv[0] rxd[0][1] bmd[6] txd[4][0] 51 127 21 txd[1][2] rxd[4][2] 117 18 37 98 142 mdc 143 35 pull_dn /test2 75 rxd[0][0] 131 txer[1] rxdv[1] 83 bma[1] bma[10] 46 90 txd[2][2] 2 84 17 109 78 txd[4][3] bmd[2] pull_dn 94 rxdv[4] rxclk[3] rxd[2][3] /half10 rxd[4][3] rxd[2][2] txer[3] 70 96 150 /bmwr 47 4 115 bma[12] vss1 col_o[4] set0 27 vss 158 rxclk[0] 74 135 rxer[4] bma[14] vdd1 AX88875AP ( mode 1 ) vdd1 28 bmd[0] 91 105 col[0] crs[0] 130 led[2] 12 151 vss 64 48 41 24 62 /rst 81 vss1 59 bmd[5] 139 txer[0] 133 141 rxd[3][0] pull_dn 111 txd[3][3] vdd1 82 43 132 49 bma[13] 76 vss 87 vss1 rxclk[1] txd[2][3] 88 146 71 159 set2 79 137 126 23 txd[1][0] /bma[15] vdd 16 3 rxd[1][1] bma[2] rxd[1][0] 45 120 rxer[0] bmd[4] 145 led[0] vss 160 rxer[2] 10 92 vdd 107 89 vss vdd bma[4] 134 93 rxdv[2] 101 42 set1 nc 13 txd[0][0] crs[4] 61 149 112 65 txd[3][0] 5 34 bma[5] 118 mclk txen[0] 56 63 32 col[2] 1 36 155 106 vdd1 bma[3] lclk crs[2] 44 50 40 col[3] 116 rxd[0][2] rxd[3][1] 129 38 114 txd[2][0] led_ck rxd[4][1] 72 67 26 bma[8] 128 140 rxer[3] bmd[7] 86 11 bma[15] vdd rxdv[3] 52 pull_dn bma[9] 7 bmd[3] rxd[1][3] 30 rxd[3][2] 8 58 bma[16] txen[2] txd[0][3] txd[0][1] 69 19 66 col[4] bma[6] rxd[1][2] 157 95 vss 6 15 136 txd[3][2] 20 bma[0] 152 110 txd[0][2] 29 156 rxclk[4] 102 txen[1] vdd pull_dn 80 103 rxer[1] 108 113 bmd[1] 99 vdd 14 22 138 85 rxd[4][0] rxd[2][1] txer[2] 68 led[1] 123 vss vdd col[1] txen[4] 122 txd[1][1] 60 /lcol100 104 53 txd[1][3] 124 /lcol10 97 121 txd[3][1] 25 nc vss 154 rxd[0][3] bma[11] txen[3] txd[4][2] rxd[3][3] mdo 73 9 147 crs[1] test1 39 100 77 31 nc nc nc nc nc nc nc nc nc nc nc nc nc
AX88875AP bripeater asix electronics corporation 8 2.0 pin description the following terms describe the ax88875a pinout: all pin names with the ? / ? suffix are asserted low. i = input o = output i/o = input /output 2.1 mii interfaces signal name type pin no. description txer[4:0] or col[4:0] o or i 66, 44, 28 9, 154 transmit error : when /half10 pin set to ? high ? . txer is transition synchronously with respect to the rising edge of txclk . asserted high when a code violation is request to be send collision : when /half10 pin set to ? low ? . col is input from phy, when 10mbps phy is in half-duplex mode. txd[4:0][3:0] o 65 ? 62, 43 ? 40 27 ? 24, 8 ? 5 153 - 150 transmit data : txd[3:0] is transition synchronously with respect to the rising edge of txclk. for each txclk period in which txen is asserted, txd[3:0] are accepted for transmission by the phy. txen[4:0] o 61, 39, 23 4, 149 transmit enable : txen is transition synchronously with respect to the rising edge of txclk. txen indicates that the port is presenting nibbles on txd [3:0] for transmission. rxd[4:0][3:0] i 60 ? 57, 37 ? 34 22 ? 19, 3, 2 160, 159, 147 - 144 receive data : rxd [3:0] is driven by the phy synchronously with respect to rxclk. rxer[4:0] i 51, 30, 15, 155, 140 receive error : rxer ,is driven by phy and synchronous to rxclk, is asserted for one or more rxclk periods to indicate to the port that an error has detected. rxclk[4:0] i 56, 33, 18, 158, 143 receive clock : rx_clk is a continuous clock that provides the timing reference for the transfer of the rxdv,rxd [3:0] and rxer signals from the phy to the mii port of the repeater. rxdv[4:0] i 52, 31, 16, 156, 141 receive data valid : rx_dv is driven by the phy synchronously with respect to rxclk. asserted high when valid data is present on rxd [3:0]. crs[4:0] i 53, 32, 17, 157, 142 carrier sense : asynchronous signal crs is asserted by the phy when receive medium is non-idle at full duplex mode. col_o[4] o 67 collision : collision detection signal for port 4
AX88875AP bripeater asix electronics corporation 9 2.2 led display signal name type pin no. description led[2:0] or /luti[2:0] o 76 - 74 led display information : when mode= ? 1 ? , those signals indicate each port ? s partition, jabber, activity, collision (global), repeater id, utilization % (global), collision % (global) in sequence. for detail , see the led timing specification /luti[2:0] : when mode= ? 0 ? , those pins drive utilization[2:0] leds directly. the utilization % display define as following : (see note 1 also) the collision % display define as following : led_ck or /luti[3] o 77 led clock signal : when mode= ? 1 ? , the signal is a discontinue clock for led signals serial shift out. the clock period width is 40ns and last 16 cycle with every 125ms repeated. /luti[3] : when mode= ? 0 ? , this pin drive utilization[3] led directly. /lcol10 or /luti[4] o/z 113 collision led for 10mbps : when mode= ? 1 ? , this pin indicates 10mbps repeater collision occurred. /luti[4] : when mode= ? 0 ? , this pin drive utilization[4] led directly. nc or /luti[5] o 112 nc : when mode= ? 1 ? , the pin function is reserved. /luti[5] : when mode= ? 0 ? , this pin drive utilization[5] led directly. /lcol100 o/z 69 collision led for 100mbps : this pin indicates 100mbps repeater collision occurred. nc or /lact[4:0] o 121, 124 123, 128 127 nc : when mode= ? 1 ? , the pin function is reserved. /lact[4:0] : when mode= ? 0 ? ,those pins drive activity[4:0] leds directly. nc or /lpart[4:0] o/oc 119-115 nc : when mode= ? 1 ? , the pin function is reserved. or /lpart[4:0] : when mode= ? 0 ? , those pins drive partition[4:0] leds directly. collision % led0 led1 led2 led3 led4 led5 led6 led7 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 2 0 0 1 1 1 1 1 1 5 0 0 0 1 1 1 1 1 10 0 0 0 0 1 1 1 1 15 0 0 0 0 0 1 1 1 20 0 0 0 0 0 0 1 1 30 0 0 0 0 0 0 0 1 60+ 0 0 0 0 0 0 0 0 utilization % led0 led1 led2 led3 led4 led5 led6 led7 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 5 0 0 1 1 1 1 1 1 10 0 0 0 1 1 1 1 1 15 0 0 0 0 1 1 1 1 30 0 0 0 0 0 1 1 1 40 0 0 0 0 0 0 1 1 60 0 0 0 0 0 0 0 1 80+ 0 0 0 0 0 0 0 0
AX88875AP bripeater asix electronics corporation 10 note : the utilization % display define as following for mode 0 led direct driving. note 1 : the calculation formulas of traffic utilization between asix and netcom is difference, so you will get different results when using smartbit (sb) testing this item. we found the smartbit calculate the utilization without include 96 bit time inter frame gap. so the utilization value can be 100%. as well as we found sb used min packet size (64 byte) and min ifg (96 bit-time) as 100% utilization. in theory, when max packet size(1518 byte) and min ifg the utilization will be more than 100%, but sb also treat it as 100%. in our ax88875 design, we use real cable bandwidth as calculation base. we calculate the bit counts of carrier within a unit time. because of the existence of inter frame gap, in our calculation 100% utilization is impossible. so the above two cases (64 byte packet size and 1518 byte packet size with min. ifg ), we will count as 85.7% and 99.2%. if using sb test result to indicate utilization led the value must be modified. see the following reference table. asix ? s utilization% 1 5 10 15 30 60 smartbit ? s utilization% 2 7 12 17 34 68 2.3 buffer memory pins group signal name type pin no. description bma[16:0] o 88-82, 80, 79, 107-104, 102-99 b uffer address bus. bmd[7:0] i/o 97-90 b uffer data bus . /bmwr i/o 78 m emory control pin for write. /bma[15] i/o 73 invert b uffer address 15. utilization % /luti0 /luti1 /luti2 /luti3 /luti4 /luti5 0 1 1 1 1 1 1 1 0 1 1 1 1 1 5 0 0 1 1 1 1 10 0 0 0 1 1 1 15 0 0 0 0 1 1 30 0 0 0 0 0 1 60 0 0 0 0 0 0
AX88875AP bripeater asix electronics corporation 11 2.4 miscellaneous signal name type pin no. description lclk i 133 local clock : must be run at 25mhz . used for transmit data to phy devices, /rst i 131 reset : the chip is reset when this signal is asserted low. nc or /lsel10 i/pu 110 nc : no connection when mode= ? 1 ? . /lsel10 : when mode= ? 0 ? , this pin select 10mbps global led status ( utilization (%) and collision (%) ) when ? low ? ; otherwise , 100mbps led status is selected. nc or /lcol10 o/ml 111 nc : no connection when mode= ? 1 ? . /lcol : when mode= ? 0 ? , this pin drives 10mbps collision led directly. mclk o 72 mii clock out : 2.5mhz 10mbps mii reference clock mdo o 71 station management data out : for setup phy auto-negotiation registers. a burst write commands are issue to setup phy register after reset. the phy address 4h, 5h, 6h, 7h, 8h, 9h,ah and bh will be written as register 4h to value 00a1h ( advertise register set to 10/100 half-duplex mode)and register 0h to value 1000h(enable auto-negotiation). mdc o 70 station management data clock out : for mdo reference clock. test1 i/pd 130 test pin : the pin is just for test mode setting purpose only. must be pull low when normal operation. /test2 i/pu 114 test pin : the pin is just for test mode setting purpose only. must be pull high when normal operation. /half10 i/pu 134 half-duplex mode in 10mbps : pull low with 10k ohm resister for 10mbps phy in half-duplex mode. pull_dn i 11, 12, 46 136, 137 pull down : those pins are not use for application. designer must pull them down or tie to ground. set2, set1, set0 o 49, 48, 47 setup pins : those pins are power on configuration use. default internal pull high. if necessary, pull low with 10k ohm resister. tie to ground is prohibited. vdd i 1, 13, 38 50, 55, 81 103, 109 125, 135 138 power : +5v +/-5% vss i 10, 14, 29 45, 54, 68 89, 98, 108, 120, 132, 139 148, power: 0v
AX88875AP bripeater asix electronics corporation 12 2.5 power on configuration setup signals cross reference table signal name share with description opt[4] col_o[4] opt[4] : option for external device type to connect to port 4. default ? high ? is for phy type device. otherwise, ? low ? for bridge, switch or mac type device. txm_mode set2 txm_ mode : option for internal used. default ? high ? user may pull the pin ? low ? with 10k ohm resister for reserve transmition mode alternaty. mode set1 mode = 0 : direct led display mode. mode = 1 : rich led display mode. en_flow_ctl set0 en_flow_ctl = 0 : disable flow control function. en_flow_ctl = 1 : enable flow control function. st_fw txd[4][3] st_fw = 0 : fragment free forwording mode. st_fw = 1 : store & forword forwording mode. entries txd[4][2] entries = 0 : 1024 entries supported entries = 1 : 256 entries supported mem_size[1] mem_size[0] txd[4][1] txd[4][0] mem_size[1] mem_size[0] size (k) 1 1 32k 1 0 64k 0 1 128k 0 0 n/a /ir_act_en /bmwr inter repeater active input pin enable : designer must keep the pin pull high to disable the function. all of the above signals are pull-up for default values.
AX88875AP bripeater asix electronics corporation 13 3.0 functional description 3.1 repeater state machine the repeater state machine is used to control repeater behavior , generates right signal in corresponding states. the repeater state machine is in idle state when there is no carrier presented on any ports . when there is only one port has receive activity, the repeater state machine will enter data - forwarding state to ensure correct data forwarding to other connected ports. if collision happens anytime , the repeater state machine detects collision then send jam pattern to all ports until collision ceases. idle state the idle state happens when these conditions exists: a. /rst is low. b. all crs[4:0] are not asserted high in single chip application. data forwarding state the state happens when the condition exists: a. only one signal asserted among crs[4:0] in single chip application. the repeater state machine stores receiving packet and transmits to all other ports except for 1. the port is jabbered. 2. the port is isolated. collision state the collision state happens when these conditions exists: a. there are two or more signals asserted high among crs[4:0] in single chip system. b. only one carrier exists but rxdv still low exceeds 4 clock cycles in 100base-t. the repeater sends collision pattern to all ports. one port left state the state happens only when there is no collision but still one port which experienced collision has receive activity. the repeater remains send collision pattern to all ports except the port. 3.2 rxe /txe control idle state the repeater sends no data to any port. rxe(all) = 0. txe(all) = 0. data forwarding state if active(x) = 1, x is the local connected port, rxe(x) = 1, rxe(all-x) = 0. txe(x) = 0, txe(all-x) = 1. collision state the repeater sends jam pattern to all ports. rxe(all) = 0. txe(all) = 1. one port left state the repeater sends jam pattern to all other port except for the still activity port. rxe(all) = 0. txe(all-x) = 1. suppose x is the one left port.
AX88875AP bripeater asix electronics corporation 14 3.3 jabber state machine to prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber timer. if a reception exceeds this duration (64k bit times for ax88875a) , the jabber condition will be detected. in this condition, repeater unit will disable receive and transmit packets for the jabbered port and the other ports remain the normal operation. when the carrier is no longer detected for the jabbered port or reset the repeater, the jabber function will be clear and re-enable reception and transmission. 3.4 partition state machine the partition state machine is used to protect network from being upset when a port suffer continuous collision, each port uses a partition state machine to detect and prevent this condition. when a port suffer from continuous 64 times of collision events, then it goes to partition state. the partitioned port will be not released until a packet without collision be transmitted( more than 512 bit times for ax88875a) or reset the repeater. 3.5 led display interface ax88875a provides per-port led status indication for partition, jabber, activity and support rate - based led for global partition and collision, utilization (%) for 10/100mbps. .detail function is described on the previous pin description(led interface). led[2:0] are all active low. there are two display ways : complicated and simple way. it depends on the setting of mode. rich led display application (mode = 1) led[2:0] status driver wave-form as follows : jab4 jab3 jab2 jab1 jab0 part 4 led_ck led[0] '0' 100m gcol 10m gcol led[1] led[2] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 d13 d14 d10 d15 part 0 part 1 part 2 part 3 act 0 act 1 act 2 act 3 act 4 10m uti7 10m uti0 10m uti1 10m uti2 10m uti3 10m uti4 10m uti5 10m uti6 100m uti7 100m uti0 100m uti2 100m uti3 100m uti4 100m uti5 100m uti6 100m uti1 g part ram fail
AX88875AP bripeater asix electronics corporation 15 notes: a. part4~0indicates partition status for each port b. jab4~0 indicates jabber status for each port c. act4~0 indicates activity status for each port d. rid2~0 is the id of repeater chip e. 10m uti4~0 indicate global utilization rate of f. 100m uti4~0 indicate global utilization rate of 10mbps for each 104.8ms sampling period. 100mbps for each 104.8ms sampling period. g. 10m gcol indicate global collision h. 100m gcol indicate global collision i. gpart : indicate global partition. j. ram fail : bridge ram test fail. it must use external shift register to decode data on led[2:0]. the application shows as follows: 74ls164(#1) 74ls164(#2) q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 d d q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 part0 part1 part2 part3 part4 jab0 jab1 jab2 jab3 jab4 led[0] led_ck fig - 4 application for led display if the user don ? t want to show jabber status, take away the latter 74ls164(#2). the application is the same for led[2:1]. simple led display application (mode=0) led display for mode 1 vs. mode 0 referance table. mode 1 mode 0 mode 1 mode 0 mode 1 mode 0 nc /part[0] nc /act[0] led[0] /uti[0] nc /part[1] nc /act[1] led[1] /uti[1] nc /part[2] nc /act[2] led[2] /uti[2] nc /part[3] nc /act[3] led_ck /uti[3] nc /part[4] nc /act[4] nc /uti[4] nc /uti[5] nc /lcol10 /lcol100 /lcol100
AX88875AP bripeater asix electronics corporation 16 4.0 internal registers 4.1 configuration register (config) bit bit name access bit description d9 /half10 r/w half-duplex mode in 10mbps : ? low ? resister to 10mbps phy in half- duplex mode. ? high ? resister to 10mbps phy in full-duplex mode. d8 opt[4] r/w opt[4] : option for external device type to connect to port 4. default ? high ? is for phy type device. otherwise, ? low ? for bridge, switch or mac type device. d7 txm_mode r/w txm_ mode : option for internal used. default ? high ? user may pull the pin ? low ? with 10k ohm resister for reserve transmition mode alternaty. d6 mode r/w mode = 0 : single chip repeater application. mode = 1 : multiple chips cascaded repeater application. d5 en_flow_ ctl r/w en_flow_ctl = 0 : disable flow control function. en_flow_ctl = 1 : enable flow control function. d4 st_fw r/w st_fw = 0 : fragment-free mode st_fw =1 : store-n-forward mode d3 entries r/w entries = 0 : 1024 entries supported entries = 1 : 256 entries supported d2-1 mem_size[1] mem_size[0] r/w mem_size[1] mem_size[1] size (k) 1 1 32k 1 0 64k 0 1 128k 0 0 n/a d0 /ir_act_en r/w inter repeater active input pin enable : designer must keep the pin pull high to disable the function.
AX88875AP bripeater asix electronics corporation 17 5.0 electrical specification and timing 5.1 absolute maximum ratings description sym min max units operating temperature ta 0 +70 c storage temperature ts -55 +150 c supply voltage vcc -0.5 +7 v input voltage vin vss-0.5 vdd+0.5 v output voltage vout vss-0.5 vdd+0.5 v lead temperature (soldering 10 seconds maximum) tl -55 +235 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability 5.2 general operation conditions description sym min max units operating temperature ta 0 +70 c supply voltage vdd +4.75 +5.25 v 5.3 dc characteristics (vdd=4.75v to 5.25v, vss=0v, ta=0 c to 70 c) description sym min max units low input voltage vil vss-0.5 0.8 v high input voltage vih 2 vdd+0.5 v low output voltage vol 0.4 v high output voltage voh 2.4 v input leakage current 1 (note 1) iil1 10 ua input leakage current 2 (note 2) iil1 500 ua output leakage current iol 10 ua description sym min tpy max units power consumption pc 120 160 ma note : 1. all the input pins without pull low or pull high. 2. those pins had been pull low or pull high.
AX88875AP bripeater asix electronics corporation 18 5.4 ac specifications 5.4.1 mii interface timing tx & rx t0 t1 lclk t2 t2 tx_en t3 t3 tx_er txd symbol description min typ. max units t0 local clock cycle time 39.996 40 40.004 ns t1 local clock high time 14 20 26 ns t2 tx_en delay from lclk high 7.440 21.760 ns t3 tx_er or txd delay from lclk high 3.410 13.320 ns t4 t5 rx_clk crs t6 t7 rxe t8 rxdv t9 rxd rxer
AX88875AP bripeater asix electronics corporation 19 symbol description min typ. max units t4 rx_clk clock cycle time 39.996 40 40.004 ns t5 rx_clk clock high time 14 20 26 ns t6 crs to rxe assertion delay 20 ns t7 crs to rxe de-assertion delay 160 200 ns t8 crs to rxdv delay requirement 40 160 ns t9 rxd or rxdv or rx_er setup to rx_clk rise time 10 - ns 5.4.2 sram read cycle and write cycle bma[16:0] /bmwr bmd[7:0] symbol description min max units t1 read cycle time 40 - ns t2 bmd[7:0] setup time 3 - ns t3 bmd[7:0] hold time 3 - ns bma[16:0] /bmwr bmd[7:0] symbol description min max units t4 write cycle time 38 - ns t5 write pulse wtdth 20 - ns t6 bmd[7:0] data valid to end of write 14 - ns t7 bmd[7:0] data hold from end of write 1 ns t1 t3 t2 t4 t7 t5 t6
AX88875AP bripeater asix electronics corporation 20 5.4.3 led display t3 led_ck -------- - ~ ~ ------- d0 d1 d2 .............. d14 d15 d0 d1 d2 t4 t3 led_ck t1 t2 led[2:0] d0 d1 d2 d3 ------- d15 d0 symbol description min typ. max units t1 led setup to led_ck high 190 200 ns t2 led hold from led_ck high 200 210 ns t3 led_ck period width 400 ns t4 continuous 16 led_ck cycle time 52.4 ms 5.4.4 led display after reset /reset t1 t2 t2 t2 t3 led[2:0] symbol description min typ. max units t1 repeater reset time 1000 ns t2 led blink time after reset 838.4 ms t3 led dark time before normal display 419.2 ms
AX88875AP bripeater asix electronics corporation 21 6.0 package information b e d hd e he pin 1 a2 a1 l l1 q milimeter symbol min. nom max a1 0.25 a2 3.15 3.40 3.65 b 0.22 0.30 0.38 d 27.90 28.00 28.10 e 27.90 28.00 28.10 e 0.65 hd 30.95 31.20 31.45 he 30.95 31.20 31.45 l 0.73 1.03 l1 1.60 q 0 7
AX88875AP bripeater asix electronics corporation 22 appendix a : applications two type of applications for ax88875a are illustrated bellow. a.1 stand-along 5-ports 10/100mbps hub application fig - 5 stand-along 5-ports 10/100mbps hub application a.2 stand-along 4-ports 10/100mbps hub with one mac application fig - 6 stand-along 4-ports 10/100mbps hub with one mac application ax88875a bripeater controller mii interface mii interface single mii transceiver 8 bits sram quad mii transceiver led array ax88875a bripeater controller mii interface mii interface ax88195 mac 8 bits sram quad mii transceiver led array cpu
AX88875AP bripeater asix electronics corporation 23 appendix b : using mii i/f connects to mac using mii interface to connect to mac type device application for ax88875a is illustrated bellow. 10k gnd ax88875 / repeater ax88195 / mac note : 1. the mac needs to run at halfduplex mode. 2. care must be taken that the receive side has enough setup and/or hold time 3. some kind of cpu with embbeded mac can also refer to this example using mii interface to connect to 10mbps mac device application for ax88875a is illustrated bellow. 10k gnd ax88875 / repeater 10mbps mac col_o4 txen4 (lclk) txd4[3:0] txer4 crs4 rxdv4 rxclk4 rxd4[3:0] rxer4 col crs rx_dv rx_clk rxd[3:0] rx_er tx_en tx_clk txd[3:0] tx_er 25mhz clock col_o4 txen4 mclk txd4[3:0] txer4 crs4 rxdv4 rxclk4 rxd4[3:0] rxer4 col crs rx_dv rx_clk rxd[3:0] rx_er tx_en tx_clk txd[3:0] tx_er

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